https:\/\/webconf.imt.fr\/frontend\/rooms\/e2b-mut-25i-kmp\/join<\/a><\/p>\n\n\n\nMembres du jury :<\/strong><\/p>\n\n\n\nM. Ga\u00ebl THOMAS<\/strong>, Directeur de recherche, Inria Saclay, FRANCE – Directeur de th\u00e8se
M. Mathieu BACOU<\/strong>, Ma\u00eetre de conf\u00e9rences, T\u00e9l\u00e9com SudParis, FRANCE – Co-encadrant de th\u00e8se
M. Pierre SENS<\/strong>, Professeur, Sorbonne Universit\u00e9, FRANCE – Rapporteur
M. Daniel HAGIMONT<\/strong>, Professeur, Universit\u00e9 de Toulouse, FRANCE – Rapporteur
M. Guillermo POLITO<\/strong>, Charg\u00e9 de recherche, Inria Lille , FRANCE – Examinateur
Mme Sara BOUCHENAK<\/strong>, Professeure, INSA Lyon , FRANCE – Examinatrice<\/p>\n\n\n\n\u00ab Collecter de tr\u00e8s grands tas avec t\u00e9l\u00e9GC \u00bb<\/h2>\n\n\n\npr\u00e9sent\u00e9 par Monsieur Adam CHADER<\/h2>\n\n\n\n
R\u00e9sum\u00e9 :<\/strong><\/p>\n\n\n\nLa m\u00e9moire hi\u00e9rachique (ou m\u00e9moire \u00e0 plusieurs niveaux), est un paradigme de gestion des donn\u00e9es qui a \u00e9merg\u00e9 avec l’av\u00e8nement de nouvelles technologies m\u00e9moire (m\u00e9moire persistente, disque, High Bandwith Memory (HBM), m\u00e9moire programmable,…) et de nouveaux canaux de communication entre les m\u00e9moires (Infiniband, CXL, NUMA, …). Dans cette abstraction, chaque niveaux m\u00e9moire offre des latences diff\u00e9rentes, et des capacit\u00e9s de stockage plus ou moins \u00e9lev\u00e9es. Pour profiter des propri\u00e9t\u00e9s diff\u00e9rentes des m\u00e9moires de mani\u00e8re optimale, l’objectif des chercheurs et d\u00e9veloppeurs syst\u00e8me est de d\u00e9cider o\u00f9 placer les donn\u00e9es dans ces divers niveaux. Par exemple, il est plus efficace de placer les donn\u00e9es acc\u00e9d\u00e9es plus fr\u00e9quement dans les m\u00e9moires plus rapides comme la DRAM (Dynamic Random Access Memory) ou les caches CPU, et les donn\u00e9es les moins utilis\u00e9es dans les niveaux plus lents comme le disque, ou la m\u00e9moire distante. Notre \u00e9tude se place dans un contexte pr\u00e9cis de m\u00e9moire hierarchique appel\u00e9 la m\u00e9moire d\u00e9sagr\u00e9g\u00e9e. Dans ce contexte, les noeuds au sein d’un cluster peuvent acc\u00e9der directement \u00e0 la m\u00e9moire des autres noeuds, sans interrompre leurs processeurs. Ce proc\u00e9d\u00e9 s’appelle RDMA (acc\u00e8s m\u00e9moire direct \u00e0 distance), et permet, si la transparence est assur\u00e9e par le syst\u00e8me d’exploitation, de donner l’abstraction aux applications d’une m\u00e9moire tr\u00e8s grande, qui est en r\u00e9alit\u00e9 la somme des m\u00e9moires de tous les noeuds dans le cluster. Cependant, RDMA qui, par construction, n’impl\u00e9mente pas de coh\u00e9rence de cache, rend l’\u00e9change de donn\u00e9e entre les CPUs des diff\u00e9rents noeuds impossible. Dans les faits, le cluster est divis\u00e9 en deux groupes de noeuds, des noeuds de calculs, qui accueillent les applications, et des noeuds m\u00e9moires, qui servent de stockage distant, plus performants que le disque. Dans ce contexte, plusieurs projets de recherche ont montr\u00e9 que l’execution d’une application accompagn\u00e9e d’un ramasse miette (ou Garbage Collector (GC)), \u00e9tait particuli\u00e8rement affect\u00e9e par l’utilisation de m\u00e9moire d\u00e9sagr\u00e9g\u00e9e. Cela est du au fait que les GC poss\u00e8dent une tr\u00e8s mauvaise localit\u00e9 d’acc\u00e8s, car ils parcourent toute la m\u00e9moire pour trouver les objets \u00e0 lib\u00e9rer. La solution trouv\u00e9e dans la litt\u00e9rature a \u00e9t\u00e9 de d\u00e9placer l’\u00e9x\u00e9cution du ramasse miette vers les noeuds m\u00e9moires, dans lequels la majorit\u00e9 des objets est stock\u00e9e. Cependant, nous avons mesur\u00e9 que l’execution d’un GC sur le noeud m\u00e9moire d\u00e9grade les performances significativement \u00e0 cause de la synchronisation entre le collecteur et l’application, car les faire communiquer est maintenant bien plus co\u00fbteux. Notre contribution vise \u00e0 eviter ce co\u00fbt de synchronisation \u00e0 l’aide d’un nouveau ramasse miette appel\u00e9 TeleGC. TeleGC est localis\u00e9 sur le noeud distant, cependant, contrairement aux prototypes concurrents, nous proposons d’utiliser l’absence de coh\u00e9rence de cache \u00e0 notre avantage pour g\u00e9n\u00e9rer une capture de la m\u00e9moire sur le noeud distant. En effet, si l’on garantit qu’aucune \u00e9criture n’est effectu\u00e9e sur une r\u00e9gion de m\u00e9moire, il est possible de la collecter de mani\u00e8re ind\u00e9pendante, sans synchronisation avec l’application pour garantir l’int\u00e9grit\u00e9 de la m\u00e9moire. Pour obtenir cette capture, nous avons d\u00e9velopp\u00e9 la barri\u00e8re de write-back, qui bloque et redirige les \u00e9critures de la m\u00e9moire locale vers la m\u00e9moire distante pendant une collection. D’autre part, notre ramasse miette n’effectue pas de compaction, c’est \u00e0 dire n’aggrege pas les objets vivants restants, car cela implique une synchronisation d’autant plus importante entre le ramasse miette et l’application, tr\u00e8s couteuse dans le contexte de d\u00e9sagr\u00e9gation. Pour palier \u00e0 la fragmentation qui se g\u00e9n\u00e8re alors, nous proposons une disposition de la m\u00e9moire particuli\u00e8re, similaire \u00e0 celle de la machine virtuelle Python. Avec cette approche, notre prototype est capable de surpasser \u00e0 la fois les GCs en production de la JVM (Java Virtual Machine), et les impl\u00e9mentations de l’\u00e9tat de l’art dans un contexte d\u00e9sagr\u00e9g\u00e9.<\/p>\n\n\n\n
Abstract :<\/strong><\/p>\n\n\n\nMemory tiering has emerged in recent years as a good abstraction to account for the multiplicity of memory technologies (persistent memory, high bandwith memory (HBM), programmable memory, disk,…), and of memory communication technologies (NUMA, RDMA, CXL,…). A large portion of system research in this field has focused on transparent placement of memory in these multiple tiers that present different properties like latency and capacity. In our study, we focus on memory disaggregation, a memory tiering practice where nodes in a cluster can directly access memory in other special nodes called memory nodes. The access to these other remote memories is slower than to the local memory of the node, but allows to transparenly make application memory larger. The local memory is here used as a cache for the remote memory. In this context, several research projects have shown that the execution of a garbage collected (GC) application is greatly affected in terms of performance by the use of disaggregated memory. This is due to the fact that garbage collectors present very bad locality, as they need to parse the entire memory to determine which objects to collect. Thus, they perform poorly in the cache context that is disaggregation, and even pollute the cache, deteriorating the performance of the collected application even more. Contributions in the literature solve this problem by moving the garbage collector to the remote memory node. This way, all GC memory accesses are done directly, without transiting by the cache. Unfortunately, we measured that executing the GC on the memory node significantly degrades performance because of synchronization between the GC and the application as making them communicate is now costlier. Our contribution aims to avoid this synchronization with a garbage collector called TeleGC. TeleGC is located on the remote memory node, and removes the need for any synchronization by leveraging the absence of cache coherence between local and remote node in a disaggregated setting. Thanks to this, and with a new technique called write-back retention, we are able to obtain an immutable snapshot of the memory on the memory node during collection, which allows for safe collection without any synchronization. With this approach, we are able to outperform both production Java garbage collectors and the state of the art implementations in a disaggregated context.<\/p>\n","protected":false},"excerpt":{"rendered":"
L’Ecole doctorale : Ecole Doctorale de l’Institut Polytechnique de Paris et le Laboratoire de recherche SAMOVAR – Services r\u00e9partis, Architectures, Mod\u00e9lisation, Validation, Administration des R\u00e9seaux pr\u00e9sentent l\u2019AVIS DE SOUTENANCE de Monsieur Adam CHADER Autoris\u00e9 \u00e0 pr\u00e9senter ses travaux en vue de l\u2019obtention du Doctorat de l’Institut Polytechnique de Paris, pr\u00e9par\u00e9 \u00e0 T\u00e9l\u00e9com SudParis en : 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