Ce jeudi 4 juin 2020 \u00e0 14H00 aura lieu le 3e s\u00e9minaire mensuel de la communaut\u00e9 \u00ab\u00a0Information, communications, \u00e9lectronique\u00a0\u00bb d’IP Paris. Vous trouverez le th\u00e8me et l’orateur ci-dessous.<\/p>\n
Le s\u00e9minaire se tiendra en visio :
\nhttps:\/\/telecom-paris.zoom.us\/j\/98415803537?pwd=OE40Q0ErRnhXNDZ5VENjTHZLakFZUT09<\/p>\n
Alain Sibille et Badr-Eddine Benkelfat
\nOrganisateurs du s\u00e9minaire ICE<\/p>\n
Circuit design perspective of foundry announced MRAM<\/p>\n
Hao CAI, Southeast University, Nanjing, China et Telecom Paris (LTCI \/ SSH)
\nJeudi 4 juin 2020 \u00e0 14H<\/p>\n
Abstract:<\/strong> Magnetic random access memory (MRAM) is a novel technology of non-volatile random-access memory, developed in the eighties, based on the change of state of the spin of the electron, notably through tunneling (quantum) effect. MRAMs are often quoted as an \u00ab\u00a0ideal\u00a0\u00bb technology, combining fast switching, high data throughput and non volatile character with low energy consumption. Still, it hasn’t yet found widespread use, due to the competion with more conventional technologies such as flash RAM and DRAM semiconductor memories. The talk will show the development of MRAM and other non-volatile memories (ReRAM, FeRAM), as well as the fundamental circuits used in NVM macros. The state-of-the-art circuit design techniques for ultra low-power, energy efficient non-volatile memory will be discussed. The design challenges involved in the further development of non-volatile memory will, in particular, be highlighted, e.g., nvFlip-flop, nvSRAM, and in-memory computing.<\/p>\n Bio: <\/strong> Hao Cai received the master degree from Lund University, Sweden, in 2009 and Ph.D. degree from T\u00e9l\u00e9com Paristech, France, in 2013. From 2011 to 2014, he was involved in the European EUREKA program CATRENE-RELY for high reliability nanoscale integrated circuits and systems. He is currently an Associate Professor with the National ASIC System Engineering Center, Southeast University, Nanjing, China. He has authored or co-authored over 80 scientific papers in circuit and systems (CAS), as well as solid-state circuits (SSC) domains such as IEEE JSSC, TCAS-1, TCAS-2, TED and TNANO.<\/p>\n Dr. Cai is currently a technical committee (TC) member with IEEE Circuits and Systems society. He received the CAS Darlington best paper award nomination in 2019. He received several best paper awards in GLSVLSI, APCCAS and ESREF. Since 2019, he is the principal investigator of TFET-VLSI under \u2018National Key Research and Development Program of China\u2019, he also takes responsibility of two MRAM projects under \u2018National Natural Science Foundation of China\u2019.<\/p>\n","protected":false},"excerpt":{"rendered":" Ce jeudi 4 juin 2020 \u00e0 14H00 aura lieu le 3e s\u00e9minaire mensuel de la communaut\u00e9 \u00ab\u00a0Information, communications, \u00e9lectronique\u00a0\u00bb d’IP Paris. Vous trouverez le th\u00e8me et l’orateur ci-dessous. Le s\u00e9minaire se tiendra en visio : https:\/\/telecom-paris.zoom.us\/j\/98415803537?pwd=OE40Q0ErRnhXNDZ5VENjTHZLakFZUT09 Alain Sibille et Badr-Eddine Benkelfat Organisateurs du s\u00e9minaire ICE Circuit design perspective of foundry announced MRAM Hao CAI, Southeast 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\nHowever, foundries announced the possibility of integration of MRAMs with traditional bulk CMOS devices on – fully depleted – silicon-on-insulator (FD-SOI) and potential FinFET processes, which are advanced technologies for (high performance \/ low consumption) silicon processors. Such an integration has the potential to open vast avenues of development to improve the penetration of these combined technologies in a large number of applications.<\/p>\n